The good alternative was to use the AXI Data Mover. – The transfer commands are delivered by AXI4 Stream. – The status of transfers are delivered back by. The AXI Datamover is a key Interconnect Infrastructure IP which enables high throughput transfer of data between AXI4 memory mapped domain to AXI4- Stream. For you, you are probably looking at AXI Datamover or AXI Central DMA. ” Xilinx provides the AXI Virtual FIFO Controller core to use external.
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The command word settings are as follows:. I greatly appreciate your help. For the datamover I have an independent state machine for the cmd AXIS master that keeps on switching between idle and write states.
Your suggestions, indeed, solved the issue.
To fatamover maximum extent permitted by applicable law: It also seems like the rest of the signals are correct. We have detected your current browser version is not the latest one. All forum topics Previous Topic Next Topic. We share info about use of our site with social media, ads and analytics partners. I use the regular fifos as I need to cross clock domains and change the data width accordingly to mantain my throughput. Here is what I am trying to do with my design:.
I would really appreciate some insight on what might I do to solve the problem. Additional Resources The following information is listed for each version of the core: Have you found a solution in the meantime?
Its been almost two weeks since I have been trying to get this to datmaover. We have detected your current browser version is not the latest one. I changed my HDL code for testing purposes.
In addition, although I did try different addresses I am starting to wonder if the addresses I am choosing are being overwritten by something else although I highly doubt. Believe I ran into this before.
It’s a bit strange that the second transfer cannot be executed, since a the FSM goes through through the same steps in the second iteration as it did in the first one, so the protocol is being followed, and b as far as I understand, there’s no need to do any kind of inter-transfer [re]initialization of the DataMover block or is there?
The command word settings are as follows: I suspected that there might be something wrong with the command word I am sending but the logic analyzer data tells me otherwise from what I could tell.
I am keeping a count of the 1us clock cycles to enable datzmover to do that.
I’m facing a similar situation and I’m curious to see how datamovdr fixed it. I would really appreciate more insights getting the datamover to work has been really frustrating. If you don’t use the sts busses inside your design i. I am wondernig if something in the AXI bus in not sequencing correctly.
For the mean time I have to settle with simulation to determine what is going on. Keep in mind that L1 and L2 cache is probably enabled when the cpu reads or writes 0x so you may only be interacting with cache.
As a result, I created a bit value that is a concatenation of the bit along with a bit count which is the value I am sending to the datamover DMA over AXI-Stream. I’m sorry for the extra late reply, I was away from the lab for several weeks. After that I just use a pointer to read out the contents of memory location 0x All forum topics Previous Topic Next Topic. For some reason I could not arm the core or get it to trigger.
These commands will bypass cache and give you the actual values located in memory instead of the cached values. Thanks a lot for your timely and useful assistance. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. We have detected your current browser version is not the latest one. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Embedded Processor System Design: Have you tried validating the block design?
You have the same problem? Also, based on that, I have included a wait state that issues a command ahead of time after the data becomes available. But if the datamover is connected to sHP or sGP ports, it will be bypassing cache. Then the validation would move its width down to the datamover. Though in simulation I havent gotten to see any datamover responses. ChromeFirefoxInternet Explorer 11Safari. I found out that I was also trying the same configuration, but haven’t been able to test it because the Datamover Steam Data Width Auto is stuck at 32 even though I have a bus connected to it.
It’s the mechanism to propagate various parameters like data width. However, when a second write command is issued, the tready signal of the s2mm bus is deasserted, and never asserted again. All forum topics Previous Topic Next Topic.
AXI interconnect and DataMover – Community Forums
AXI interconnect and DataMover. Please upgrade to a Xilinx. I am trying to create a design using the AXI datamover in a Zynq design using a zedboard yet I am really struggling. Still working axk it though.
I looked into it again and seems I finally managed to get it somewhat working. The VHDL code now does the following:.